Verilog Code for Full Adder

 Hello Everyone, 

What is Full Adder ?

An Full Adder is digital/logic circuit which adds three inputs and gives two outputs. Lets see the following circuit.

The above circuit shown is of Full Adder which has three inputs, input A, B, and Cin and has two outputs SUM and Carry_out. A full adder can take 8 input cobinations of three bits each. 

See the above Truth table of Full Adder.

Output Equations for Full Adder :-

SUM = (A xor B) xor Cin

Carry_out = A.B+Cin(A xor B)

Verilog Code For Full Adder :- 

RTL :-

// Code your design here

module full_adder( A, B, Cin, S, Cout);

 input wire A, B, Cin;

 output reg S, Cout;

 always @(A or B or Cin)

  begin 

   S = A ^ B ^ Cin; 

   Cout = A&B | (A^B) & Cin; 

  end

endmodule

TestBench :-

// Code your testbench here

module full_adder_tb();

 reg A,B,Cin;

 wire S,Cout;  

 //Verilog code for the structural full adder 

 full_adder DUT ( A, B, Cin, S, Cout);

 initial begin

   A = 0;

   B = 0;

   Cin = 0;

   #5;

   A = 0;

   B = 0;

   Cin = 1;

   #5;  

   A = 0;

   B = 1;

   Cin = 0;

   #5;

   A = 0;

   B = 1;

   Cin = 1;

   #5;

   A = 1;

   B = 0;

   Cin = 0;

   #5;

   A = 1;

   B = 0;

   Cin = 1;

   #5;

   A = 1;

   B = 1;

   Cin = 0;

   #5;  

   A = 1;

   B = 1;

   Cin = 1;

   #5;  

  end

  

  initial

    begin

      $monitor("Values of A=%0d,B=%0d,Cin=%0d,S=%0d,Cout=%0d", A,B,Cin,S,Cout);

    end

      

endmodule 

For EDAPlaygroung Link is Here :-

https://www.edaplayground.com/x/Nztx